Silicon on insulator (SOI) technology replaces conventional silicon substrates with a layered silicon-insulator-silicon substrate to reduce parasitic device capacitance and improve performance. Silicon on insulator (SOI) based devices differ from conventional silicon-built devices because the silicon junction is above an electrical insulator, typically a buried oxide (BOX) layer. A reduced thickness buried oxide (BOX) layer, however, may not sufficiently reduce the parasitic capacitance caused by the proximity of an active device on the silicon layer and a substrate supporting the buried oxide (BOX) layer.
Conventional complementary metal oxide semiconductor (CMOS) technology begins with a front-end-of-line (FEOL), in which a first set of process steps are performed for fabricating active devices (e.g., negative MOS (NMOS) or positive MOS (PMOS) transistors) on a substrate (e.g., a silicon on insulator (SOI) substrate). A middle-of-line (MOL) is performed next, which is a set of process steps that connect the active devices to the back-end-of-line (BEOL) interconnects (e.g., M1, M2, M3, M4, etc.) using middle-of-line contacts. Unfortunately, parasitic capacitance may result due to a proximity of the back-end-of-line interconnects and/or the middle-of-line contacts to the transistor gates.
In particular, the parasitic capacitance is caused by significant capacitive coupling between the gates and adjacent source/drain middle-of-line contacts as well as capacitive coupling between the gates and adjacent back-end-of-line interconnects. CMOS semiconductor processes also use a substrate contact. A proximity of the substrate contact and adjacent back-end-of-line interconnects cause additional capacitive coupling. This additional capacitance causes adverse effects, such as circuit delays and circuit loses.